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general description the max15026 synchronous step-down controller oper- ates from a 4.5v to 28v input voltage range and gener- ates an adjustable output voltage from 85% of the input voltage down to 0.6v while supporting loads up to 25a. the device allows monotonic startup into a prebiased bus without discharging the output and features adap- tive internal digital soft-start. the max15026 offers the ability to adjust the switching frequency from 200khz to 2mhz with an external resis- tor. the max15026? adaptive synchronous rectification eliminates the need for an external freewheeling schottky diode. the device also utilizes the external low-side mosfet? on-resistance as a current-sense element, eliminating the need for a current-sense resis- tor. this protects the dc-dc components from damage during output overloaded conditions or output short- circuit faults without requiring a current-sense resistor. hiccup-mode current limit reduces power dissipation during short-circuit conditions. the max15026 includes a power-good output and an enable input with precise turn-on/turn-off threshold, which can be used for input supply monitoring and for power sequencing. additional protection features include sink-mode cur- rent limit and thermal shutdown. sink-mode current limit prevents reverse inductor cur- rent from reaching dangerous levels when the device is sinking current from the output. the max15026 is available in a space-saving and ther- mally enhanced 3mm x 3mm, 14-pin tdfn-ep pack- age. the max15026 operates over the extended -40? to +85? and automotive -40? to +125? temperature ranges. the max15026c is designed to provide additional mar- gin for break-before-make times. applications set-top boxes lcd tv secondary supplies switches/routers power modules dsp power supplies points-of-load regulators features 4.5v to 28v or 5v ?0% input supply range 0.6v to (0.85 x v in ) adjustable output adjustable 200khz to 2mhz switching frequency ability to start into a prebiased load lossless, cycle-by-cycle valley mode current limit with adjustable, temperature-compensated threshold sink-mode current-limit protection adaptive internal digital soft-start ?% accurate voltage reference internal boost diode adaptive synchronous rectification eliminates external freewheeling schottky diode hiccup-mode short-circuit protection thermal shutdown power-good output and enable input for power sequencing ?% accurate enable input threshold aec-q100 qualified (max15026b) max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller ________________________________________________________________ maxim integrated products 1 2 4 5 *ep 13 11 10 lx dl drv v cc en lim max15026 1 + 14 dh in 312 bst pgood 69 gnd comp 78 rt fb tdfn (3mm x 3mm) top view *ep = exposed pad. pin configuration ordering information 19-4108; rev 3; 4/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max15026betd+ -40? to +85? 14 tdfn-ep* max15026betd/v+t -40? to +85? 14 tdfn-ep* max15026cetd+ -40? to +85? 14 tdfn-ep* max15026batd+ -40? to +125? 14 tdfn-ep* MAX15026CATD+ -40? to +125? 14 tdfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. /v denotes an automotive qualified part. max15026c recommended for new designs.
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 12v, r rt = 27k , r lim = 30k , c vcc = 4.7?, c in = 1?, t a = -40? to +85? (max15026b/cetd+, max15026betd/v+), t a = t j = -40? to +125? (max15026b/catd+), unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: dissipation wattage values are based on still air with no heatsink. actual maximum power dissipation is a function of heat extraction technique and may be substantially higher. package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal consid- erations, refer to www.maxim-ic.com/thermal-tutorial . in to gnd ...............................................................-0.3v to +30v bst to gnd ............................................................-0.3v to +36v lx to gnd .................................................................-1v to +30v en to gnd................................................................-0.3v to +6v pgood to gnd .....................................................-0.3v to +30v bst to lx..................................................................-0.3v to +6v dh to lx ...............................................?-0.3v to (v bst + 0.3v) drv to gnd .............................................................-0.3v to +6v dl to gnd ................................................-0.3v to (v drv + 0.3v) v cc to gnd...............-0.3v to the lower of +6v and (v in + 0.3v) all other pins to gnd.................................-0.3v to (v cc + 0.3v) v cc short circuit to gnd ...........................................continuous drv input current.............................................................600ma pgood sink current ............................................................5ma continuous power dissipation (t a = +70?) (note 1) 14-pin tdfn-ep, multilayer board (derate 24.4mw/? above +70?) ..............................1951mw operating temperature range max15026b/cetd+, max15026betd/v+.......-40? to +85? max15026b/catd+ .......................................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units general 4.5 28 input voltage range v in v in = v cc = v drv 4.5 5.5 v quiescent supply current v fb = 0.9v, no switching 1.75 2.75 ma shutdown supply current i in_sby en = gnd 290 500 ? enable to output delay 480 ? v cc high to output delay en = v cc 375 ? v cc regulator 6v < v in < 28v, i load = 25ma output voltage v cc v in = 12v, 1ma < i load < 70ma 5.0 5.25 5.5 v v cc regulator dropout v in = 4.5v, i load = 70ma 0.28 v v cc short-circuit output current v in = 5v 100 200 300 ma v cc undervoltage lockout v cc_uvlo v cc rising 3.8 4.0 4.2 v v cc undervoltage lockout hysteresis 400 mv error amplifier (fb, comp) fb input voltage set-point v fb 585 591 597 mv fb input bias current i fb v fb = 0.6v -250 +250 na fb to comp transconductance g m i comp = ?0? 600 1200 1800 ? amplifier open-loop gain 80 db amplifier unity-gain bandwidth capacitor from comp to gnd = 50pf 4 mhz v comp-ramp minimum voltage 160 mv comp source/sink current i comp v comp = 1.4v 50 80 110 ?
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units enable (en) en input high v en_h v en rising 1.14 1.20 1.26 v en input low v en_l v en falling 0.997 1.05 1.103 v en input leakage current i leak_en v en = 5.5v -1 +1 ? oscillator switching frequency f sw r rt = 27k 540 600 660 khz 1mhz switching frequency r rt = 15.7k 0.9 1 1.1 mhz 2mhz switching frequency r rt = 7.2k 1.8 2.0 2.4 mhz switching frequency adjustment range (note 3) 200 2000 khz rt voltage v rt 1.19 1.205 1.22 v pwm ramp peak-to-peak amplitude v ramp 1.8 v pwm ramp valley v valley 0.8 v minimum controllable on-time 65 100 ns maximum duty cycle f sw = 600khz 85 88 % minimum low-side on-time r rt = 15.7k 75 110 150 ns output drivers/driver supply (drv) drv undervoltage lockout v drv_uvlo v drv rising 4.0 4.2 4.4 v drv undervoltage lockout hysteresis 400 mv low, sinking 100ma, v bst = 5v 1 3 dh on-resistance high, sourcing 100ma, v bst = 5v 1.5 4.5 low, sinking 100ma, v bst = 5.2v 1 3 dl on-resistance high, sourcing 100ma, v bst = 5.2v 1.5 4.5 sinking 4 dh peak current c load = 10nf sourcing 3 a sinking 4 dl peak current c load = 10nf sourcing 3 a dh/dl break-before-make time dh at 1v (falling) to dl at 1v (rising) 10 (18, note 5) ns dl/dh break-before-make time dl at 1v (falling) to dh at 1v (rising) 10 (20, note 6) ns soft-start soft-start duration 2048 switching cycles reference voltage steps 64 steps current limit/hiccup current-limit threshold adjustment range cycle-by-cycle valley current-limit threshold adjustment range valley limit = v lim /10 30 300 mv electrical characteristics (continued) (v in = 12v, r rt = 27k , r lim = 30k , c vcc = 4.7?, c in = 1?, t a = -40? to +85? (max15026b/cetd+, max15026betd/v+), t a = t j = -40? to +125? (max15026b/catd+), unless otherwise noted. typical values are at t a = +25?.) (note 2)
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units lim reference current i lim v lim = 0.3v to 3v (note 4) 45 50 55 ? lim reference current tempco v lim = 0.3v to 3v 2300 ppm/? number of consecutive current- limit events to hiccup 7 events soft-start timeout 4096 switching cycles soft-start restart timeout 8192 switching cycles hiccup timeout out of soft-start 4096 switching cycles peak low-side sink current limit sink limit = 1.5v, r lim = 30k (note 4) 75 mv boost boost switch resistance v in = v cc = 5v, i bst = 10ma 3 8 power-good output pgood threshold rising 90 94.5 97.5 % v fb pgood threshold falling 88 92 94.5 %v fb pgood output leakage i leak_pgd v in = v pgood = 28v, v en = 5v, v fb = 1v -1 +1 ? pgood output low voltage v pgood_l i pgood = 2ma, en = gnd 0.4 v thermal shutdown thermal-shutdown threshold temperature rising +150 ? thermal-shutdown hysteresis temperature falling 20 ? electrical characteristics (continued) (v in = 12v, r rt = 27k , r lim = 30k , c vcc = 4.7?, c in = 1?, t a = -40? to +85? (max15026b/cetd+, max15026betd/v+), t a = t j = -40? to +125? (max15026b/catd+), unless otherwise noted. typical values are at t a = +25?.) (note 2) note 2: all devices are 100% tested at room temperature and guaranteed by design over the specified temperature range. note 3: select r rt as: where f sw is in hertz. note 4: t a = +25?. note 5: 10ns for max15026b, 18ns for the max15026c. note 6: 10ns for max15026b, 20ns for the max15026c. r 17.3 10 f 1x10 )x(f rt 9 sw 7 sw = + ? () 2
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller _______________________________________________________________________________________ 5 efficiency vs. load current (max15026b/c) max15026 toc01 load current (a) efficiency (%) 810 6 2 4 10 20 30 40 50 60 70 80 90 100 0 012 v out = 3.3v v out = 1.2v v out = 5v v out = 1.8v efficiency vs. load current (v in = 12v, v cc = v drv = 5v) max15026 toc02 load current (a) efficiency (%) 10 6 8 4 2 012 v out = 3.3v v out = 1.2v v out = 5v v out = 1.8v 10 20 30 40 50 60 70 80 90 100 0 v out vs. load current max15026 toc03 load current (a) % output from nominal 10 68 4 2 012 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -1.0 v cc vs. load current max15026 toc04 load current (ma) v cc (v) 80 20 40 60 5.230 5.235 5.240 5.245 5.250 5.255 5.260 5.265 5.225 0 100 v cc line regulation max15026 toc05 v in (v) v cc (v) 25 20 15 10 5 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 4.3 030 5ma 50ma v cc vs. temperature max15026 toc06 temperature ( c) v cc (v) 60 35 10 -15 5.238 5.240 5.242 5.244 5.246 5.248 5.236 -40 85 switching frequency vs. resistance max15026 toc07 resistance (k ) switching frequency (khz) 80 60 40 20 500 1000 1500 2000 2500 0 0 100 switching frequency vs. temperature max15026 toc08 temperature ( c) switching frequency (khz) 60 35 10 -15 500 1000 1500 2000 2500 0 -40 85 r rt = 7.2k r rt = 15.7k r rt = 27k r rt = 85k supply current vs. switching frequency max15026 toc09 switching frequency (khz) supply current (ma) 1000 10 20 30 40 50 60 70 80 90 0 100 10,000 typical operating characteristics (v in = 12v, t a = +25?. the following tocs are for max15026b/c, unless otherwise noted.) (see the circuit of figure 5.)
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v in = 12v, t a = +25?. the following tocs are for max15026b/c, unless otherwise noted.) (see the circuit of figure 5.) lim reference current vs. temperature max15026 toc10 temperature ( c) lim reference current ( a) 60 35 10 -15 10 20 30 40 50 60 70 0 -40 85 sink and source current-limit thresholds vs. resistance (r ilim ) max15026 toc11 resistance (k ) current-limit thresholds (v) 60 50 40 30 20 10 -0.3 -0.2 -0.1 0 0.1 0.2 -0.4 070 sink current-limit source current-limit load transient on out max15026 toc12 400 s/div ac-coupled v out 200mv/div i out 10a 1a startup and disable from en (r load = 1.5 ) max15026 toc13 4ms/div v out 1v/div v in 5v/div pgood 5v/div startup rise time (max15026b) max15026 toc14 1ms/div v in 5v/div v out 1v/div power-down fall time max15026 toc15 4ms/div v in 5v/div v out 1v/div startup rise time (max15026c) max15026 toc16 1ms/div v in 5v/div v out 1v/div 0v output soft-start with 0.5v prebias at no load (max15026c) max15026 toc17 1ms/div v in 5v/div v out 1v/div 0.5v output prebias output short-circuit behavior monitor output voltage and current max15026 toc18 4ms/div 500mv/div 0 v out i out 20a/div 0
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller _______________________________________________________________________________________ 7 pin description pin name function 1in regulator input. bypass in to gnd with a 1? minimum ceramic capacitor. connect in to v cc when operating in the 5v ?0% range. 2v cc 5.25v linear regulator output. bypass v cc to gnd with a minimum of 4.7? low-esr ceramic capacitor to ensure stability up to the regulated rated current when v cc supplies the drive current at drv. bypass v cc to gnd when v cc supplies the device core quiescent current with a 2.2? minimum ceramic capacitor. 3 pgood open-drain power-good output. connect pgood with an external resistor to any supply voltage. 4en active-high enable input. pull en to gnd to disable the output. connect en to v cc for always-on operation. en can be used for power sequencing and as a uvlo adjustment input. 5 lim current-limit adjustment. connect a resistor from lim to gnd to adjust current-limit threshold from 30mv (r lim = 6k ) to 300mv (r lim = 60k ). see the setting the valley current limit section. 6 comp compensation input. connect compensation network from comp to fb or from comp to gnd. see the compensation section. 7fb feedback input. connect fb to a resistive divider between output and gnd to adjust the output voltage between 0.6v and (0.85 x input voltage). see the setting the output voltage section. 8rt oscillator timing resistor input. connect a resistor from rt to gnd to set the oscillator frequency from 200khz to 2mhz. see the setting the switching frequency section. 9 gnd ground 10 drv drive supply voltage. drv is internally connected to the anode terminal of the internal boost diode. bypass drv to gnd with a 2.2? minimum ceramic capacitor (see the typical application circuits ). 11 dl low-side gate-driver output. dl swings from drv to gnd. dl is low during uvlo. 12 bst boost flying capacitor. connect a ceramic capacitor with a minimum value of 100nf between bst and lx. 13 lx external inductor connection. connect lx to the switching side of the inductor. lx serves as the lower supply rail for the high-side gate driver and as a sensing input of the drain to source voltage drop of the synchronous mosfet. 14 dh high-side gate-driver output. dh swings from lx to bst. dh is low during uvlo. ?p exposed paddle. internally connected to gnd. connect ep to a large copper plane at gnd potential to improve thermal dissipation. do not use ep as the only gnd ground connection.
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 8 _______________________________________________________________________________________ functional diagram oscillator dc-dc and oscillator enable logic v ref rt en enable comparator osc_enable bandgap ok generator v cc uvlo drv uvlo thermal shutdown and ilim current gen in uvlo bgap_ok bgap_ok en_int vl_ok vdrv_ok shutdown vin_ok v ref vin_ok vin_ok i bias v bgap bgap_ok bgap_ok v drv vin_ok v bgap lim in v cc internal voltage regulator main bias current generator v ref = 0.6v v bgap = 1.24v bandgap reference ck enable g m soft-start/ soft-stop logic and hiccup logic v ref hiccup ck enable dh_dl_enable v ref v ref ck ck dh_dl_enable hiccup timeout fb1 dac_vref pwm comparator ramp generator sink current-limit comparator pgood comparator valley current-limit comparator pwm pwm control logic boost driver high- side driver low- side driver ramp gatep hiccup timeout hiccup lim/20 lim/10 comp bst dh lx drv dl gnd fb pgood gnd max15026
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller _______________________________________________________________________________________ 9 detailed description the max15026 synchronous step-down controller oper- ates from a 4.5v to 28v input voltage range and gener- ates an adjustable output voltage from 85% of the input voltage down to 0.6v while supporting loads up to 25a. as long as the device supply voltage is within 5.0v to 5.5v, the input power bus (v in ) can be as low as 3.3v. the max15026 offers adjustable switching frequency from 200khz to 2mhz with an external resistor. the adjustable switching frequency provides design flexi- bility in selecting passive components. the max15026 adopts an adaptive synchronous rectification to elimi- nate an external freewheeling schottky diode and improve efficiency. the device utilizes the on-resis- tance of the external low-side mosfet as a current- sense element. the current-limit threshold voltage is resistor-adjustable from 30mv to 300mv and is temper- ature-compensated, so that the effects of the mosfet r ds(on) variation over temperature are reduced. this current-sensing scheme protects the external compo- nents from damage during output overloaded condi- tions or output short-circuit faults without requiring a current-sense resistor. hiccup-mode current limit reduces power dissipation during short-circuit condi- tions. the max15026 includes a power-good output and an enable input with precise turn-on/-off threshold to be used for monitoring and for power sequencing. the max15026 features internal digital soft-start that allows prebias startup without discharging the output. the digital soft-start function employs sink current limit- ing to prevent the regulator from sinking excessive cur- rent when the prebias voltage exceeds the programmed steady-state regulation level. the digital soft-start feature prevents the synchronous rectifier mosfet and the body diode of the high-side mosfet from experiencing dangerous levels of current while the regulator is sinking current from the output. the max15026 shuts down at a junction temperature of +150? to prevent damage to the device. dc-dc pwm controller the max15026 step-down controller uses a pwm volt- age-mode control scheme (see the functional diagram ). control-loop compensation is external for providing max- imum flexibility in choosing the operating frequency and output lc filter components. an internal transconduc- tance error amplifier produces an integrated error volt- age at comp that helps to provide higher dc accuracy. the voltage at comp sets the duty cycle using a pwm comparator and a ramp generator. on the rising edge of an internal clock, the high-side n-channel mosfet turns on and remains on until either the appropriate duty cycle or the maximum duty cycle is reached. during the on- time of the high-side mosfet, the inductor current ramps up. during the second-half of the switching cycle, the high-side mosfet turns off and the low-side n-chan- nel mosfet turns on. the inductor releases the stored energy as the inductor current ramps down, providing current to the output. under overload conditions, when the inductor current exceeds the selected valley current- limit threshold (see the current-limit circuit (lim) sec- tion), the high-side mosfet does not turn on at the subsequent clock rising edge and the low-side mosfet remains on to let the inductor current ramp down. internal 5.25v linear regulator an internal linear regulator (v cc ) provides a 5.25v nomi- nal supply to power the internal functions and to drive the low-side mosfet. connect in and v cc together when using an external 5v ?0% power supply. the maximum regulator input voltage (v in ) is 28v. bypass in to gnd with a 1? ceramic capacitor. bypass the output of the linear regulator (v cc ) with a 4.7? ceramic capac- itor to gnd. the v cc dropout voltage is typically 125mv. when v in is higher than 5.5v, v cc is typically 5.25v. the max15026 also employs an undervoltage lockout circuit that disables the internal linear regulator when v cc falls below 3.6v (typ). the 400mv uvlo hysteresis prevents chattering on power-up/power-down. the internal v cc linear regulator can source up to 70ma to supply the ic, power the low-side gate driver, recharge the external boost capacitor, and supply small external loads. the current available for external loads depends on the current consumed by the mosfet gate drivers. for example, when switching at 600khz, a mosfet with 18nc total gate charge (at v gs = 5v) requires (18nc x 600khz) = 11ma. the internal control functions consume 5ma maximum. the current available for external loads is: (70 ?(2 x 11) ?5)ma ? 43ma mosfet gate drivers (dh, dl) dh and dl are optimized for driving large-size n-chan- nel power mosfets. under normal operating condi- tions and after startup, the dl low-side drive waveform is always the complement of the dh high-side drive waveform, with controlled dead-time to prevent cross- conduction or shoot-through. an adaptive dead-time circuit monitors the dh and dl outputs and prevents the opposite-side mosfet from turning on until the other mosfet is fully off. thus, the circuit allows the high-side driver to turn on only when the dl gate driver has turned off, preventing the low-side (dl) from turn- ing on until the dh gate driver has turned off.
max15026 the adaptive driver dead-time allows operation without shoot-through with a wide range of mosfets, minimiz- ing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from dl and dh to the mosfet gates for the adaptive dead-time circuits to function properly. the stray impedance in the gate discharge path can cause the sense circuitry to inter- pret the mosfet gate as off while the v gs of the mosfet is still high. to minimize stray impedance, use very short, wide traces. synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side schottky catch diode with a low-resistance mosfet switch. the max15026 features a robust internal pulldown transis- tor with a typical 1 r ds(on) to drive dl low. this low on-resistance prevents dl from being pulled up during the fast rise time of the lx node, due to capacitive cou- pling from the drain to the gate of the low-side synchro- nous rectifier mosfet. high-side gate-drive supply (bst) and internal boost switch an internal switch between bst and dh turns on to boost the gate voltage above v in providing the neces- sary gate-to-source voltage to turn on the high-side mosfet. the boost capacitor connected between bst and lx holds up the voltage across the gate driver dur- ing the high-side mosfet on-time. the charge lost by the boost capacitor for delivering the gate charge is replenished when the high-side mosfet turns off and lx node goes to ground. when lx is low, an internal high-voltage switch connected between v drv and bst recharges the boost capacitor. see the boost capacitor section in the applications information to choose the right size of the boost capacitor. enable input (en), soft-start, and soft-stop drive en high to turn on the max15026. a soft-start sequence starts to increase step-wise the reference voltage of the error amplifier. the duration of the soft- start ramp is 2048 switching cycles and the resolution is 1/64th of the steady-state regulation voltage allowing a smooth increase of the output voltage. a logic-low on en initiates a soft-stop sequence by stepping down the reference voltage of the error amplifier. after the soft- stop sequence is completed, the mosfet drivers are both turned off. see figure 1. connect en to v cc for always-on operation. owing to the accurate turn-on/-off thresholds, en can be used as uvlo adjustment input, and for power sequencing together with the pgood output. when the valley current limit is reached during soft-start the max15026 regulates to the output impedance times the limited inductor current and turns off after 4096 clock cycles. when starting up into a large capacitive load (for example) the inrush current will not exceed the current-limit value. if the soft-start is not completed before 4096 clock cycles, the device will turn off. the device remains off for 8192 clock cycles before trying to soft-start again. this implementation allows the soft- start time to be automatically adapted to the time nec- essary to keep the inductor current below the limit while charging the output capacitor. power-good output (pgood) the max15026 includes a power-good comparator to monitor the output voltage and detect the power-good threshold, fixed at 94.5% of the nominal fb voltage. the open-drain pgood output requires an external pullup resistor. pgood sinks up to 2ma of current while low. pgood goes high (high-impedance) when the regula- tor output increases above 94.5% of the designed nom- inal regulated voltage. pgood goes low when the regulator output voltage drops to below 92% of the nominal regulated voltage. pgood asserts low during hiccup timeout period. startup into a prebiased output when the max15026 starts into a prebiased output, dh and dl are off so that the converter does not sink cur- rent from the output. dh and dl do not start switching until the pwm comparator commands the first pwm pulse. the first pwm pulse occurs when the ramping reference voltage increases above the fb voltage. low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 10 ______________________________________________________________________________________
current-limit circuit (lim) the current-limit circuit employs a valley and sink cur- rent-sensing algorithm that uses the on-resistance of the low-side mosfet as a current-sensing element, to eliminate costly sense resistors. the current-limit circuit is also temperature compensated to track the on-resis- tance variation of the mosfet over temperature. the current limit is adjustable with an external resistor at lim, and accommodates mosfets with a wide range of on-resistance characteristics (see the setting the valley current limit section). the adjustment range is from 30mv to 300mv for the valley current limit, corre- sponding to resistor values of 6k to 60k . the valley current-limit threshold across the low-side mosfet is precisely 1/10th of the voltage at lim, while the sink current-limit threshold is 1/20th of the voltage at lim. valley current limit acts when the inductor current flows towards the load, and lx is more negative than gnd during the low-side mosfet on-time. if the magnitude of current-sense signal exceeds the valley current-limit threshold at the end of the low-side mosfet on-time, the max15026 does not initiate a new pwm cycle and lets the inductor current decay in the next cycle. the controller also rolls back the internal reference voltage so that the controller finds a regulation point deter- mined by the current-limit value and the resistance of the short. in this manner, the controller acts as a con- stant current source. this method greatly reduces inductor ripple current during the short event, which reduces inductor sizing restrictions, and reduces the possibility for audible noise. after a timeout, the device goes into hiccup mode. once the short is removed, the internal reference voltage soft-starts back up to the nor- mal reference voltage and regulation continues. max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller ______________________________________________________________________________________ 11 v cc b cd e 2048 clk cycles 2048 clk cycles f g hi a uvlo en v out dac_vref dh dl uvlo undervoltage threshold value is provided in the electrical characteristics table. internal 5.25v linear regulator output. active-high enable input. regulator output voltage. regulator internal soft-start and soft-stop signal. regulator high-side gate-driver output. regulator low-side gate-driver output. v cc rising while below the uvlo threshold. en is low. v cc en v out dac_vref dh dl a symbol definition b v cc is higher than the uvlo threshold. en is low. en is pulled high. dh and dl start switching. normal operation. v cc drops below uvlo. v cc goes above the uvlo threshold. dh and dl start switching. normal operation. en is pulled low. v out enters soft-stop. en is pulled high. dh and dl start switching. normal operation. v cc drops below uvlo. c d e f g h i symbol definition figure 1. power-on/-off sequencing
max15026 sink current limit is implemented by monitoring the volt- age drop across the low-side mosfet when lx is more positive than gnd. when the voltage drop across the low-side mosfet exceeds 1/20th of the voltage at lim at any time during the low-side mosfet on-time, the low-side mosfet turns off, and the inductor current flows from the output through the body diode of the high- side mosfet. when the sink current limit activates, the dh/dl switching sequence is no longer complementary. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current- sense signals at lx and gnd. mount the max15026 close to the low-side mosfet with short, direct traces making a kelvin-sense connection so that trace resis- tance does not add to the intended sense resistance of the low-side mosfet. hiccup-mode overcurrent protection hiccup-mode overcurrent protection reduces power dis- sipation during prolonged short-circuit or deep overload conditions. an internal three-bit counter counts up on each switching cycle when the valley current-limit threshold is reached. the counter counts down on each switching cycle when the threshold is not reached, and stops at zero (000). the counter reaches 111 (= 7 events) when the valley mode current-limit condition persists. the max15026 stops both dl and dh drivers and waits for 4096 switching cycles (hiccup timeout delay) before attempting a new soft-start sequence. the hiccup-mode protection remains active during the soft- start time. undervoltage lockout the max15026 provides an internal undervoltage lockout (uvlo) circuit to monitor the voltage on v cc . the uvlo circuit prevents the max15026 from operating when v cc is lower than v uvlo . the uvlo threshold is 4v, with 400mv hysteresis to prevent chattering on the rising/falling edge of the supply voltage. dl and dh stay low to inhibit switching when the device is in undervoltage lockout. thermal-overload protection thermal-overload protection limits total power dissipation in the max15026. when the junction temperature of the device exceeds +150?, an on-chip thermal sensor shuts down the device, forcing dl and dh low, allowing the device to cool. the thermal sensor turns the device on again after the junction temperature cools by 20?. the regulator shuts down and soft-start resets during thermal shutdown. power dissipation in the ldo regulator and excessive driving losses at dh/dl trigger thermal-over- load protection. carefully evaluate the total power dissi- pation (see the power dissipation section) to avoid unwanted triggering of the thermal-overload protection in normal operation. applications information effective input voltage range the max15026 operates from input supplies up to 28v and regulates down to 0.6v. the minimum voltage con- version ratio (v out /v in ) is limited by the minimum con- trollable on-time. for proper fixed-frequency pwm operation, the voltage conversion ratio must obey the following condition, where t on(min) is 125ns and f sw is the switching fre- quency in hertz. pulse-skipping occurs to decrease the effective duty cycle when the desired voltage conver- sion does not meet the above condition. decrease the switching frequency or lower v in to avoid pulse skipping. the maximum voltage conversion ratio is limited by the maximum duty cycle (d max ): where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pcb resistance. v drop2 is the sum of the resistance in the charging path, including high-side switch, inductor, and pcb resistance. in practice, provide adequate margin to the above condi- tions for good load-transient response. setting the output voltage set the max15026 output voltage by connecting a resistive divider from the output to fb to gnd (figure 2). select r 2 from between 1k and 50k . calculate r 1 with the following equation: where v fb = 0.591v (see the electrical characteristics table) and v out can range from 0.591v to (0.85 x v in ). resistor r 1 also plays a role in the design of the type iii compensation network. review the values of r 1 and r 2 when using a type iii compensation network (see the type iii compensation network (see figure 4) section). rr v v out fb 12 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? v v d dv (1d)v v out in max max drop2 max drop1 in < + ? ? v v tf out n on(min) sw i > low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 12 ______________________________________________________________________________________
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller ______________________________________________________________________________________ 13 setting the switching frequency an external resistor connecting rt to gnd sets the switching frequency (f sw ). the relationship between f sw and r rt is: where f sw is in hz and r rt is in . for example, a 600khz switching frequency is set with r rt = 27.2k . higher frequencies allow designs with lower inductor values and less output capacitance. peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase. inductor selection three key inductor parameters must be specified for operation with the max15026: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dc ). to determine the inductance value, select the ratio of inductor peak-to-peak ac current to dc average current (lir) first. for lir values which are too high, the rms currents are high, and therefore i 2 r losses are high. use high-valued inductors to achieve low lir val- ues. typically, inductance is proportional to resistance for a given package type, which again makes i 2 r losses high for very low lir values. a good compromise between size and loss is a 30% peak-to-peak ripple cur- rent to average-current ratio (lir = 0.3). the switching frequency, input voltage, output voltage, and selected lir determine the inductor value as follows, where v in , v out , and i out are typical values (so that efficiency is optimum for typical conditions). the switch- ing frequency is set by r rt (see the setting the switching frequency section). the exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak cur- rents. on the other hand, higher inductance increases efficiency by reducing the rms current. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the satura- tion current rating (i sat ) must be high enough to ensure that saturation can occur only above the maximum cur- rent-limit value (i cl(max) ), given the tolerance of the on- resistance of the low-side mosfet and of the lim reference current (i lim ). combining these conditions, select an inductor with a saturation current (i sat ) of: i sat 1.35 x i cl(typ ) where i cl(typ) is the typical current-limit set-point. the factor 1.35 includes r ds(on) variation of 25% and 10% for the lim reference current error. a variety of inductors from different manufacturers are available to meet this requirement (for example, coilcraft mss1278-142ml and other inductors from the same series). setting the valley current limit the minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side mosfet on-resistance value as the r ds(on) of the low-side mosfet is used as the current-sense element. the inductor? valley cur- rent occurs at i load(max) minus one half of the ripple current. the minimum value of the current-limit thresh- old voltage (v ith ) must be higher than the voltage on the low-side mosfet during the ripple-current valley: where r ds(on) is the on-resistance of the low-side mosfet in ohms. use the maximum value for r ds(on) from the data sheet of the low-side mosfet. vr i lir ith ds on max load max > ? ? ? ? ? ? ? (, ) ( ) 1 2 l vvv vf i lir out in out in sw out = ? () r 17.3 10 f 1x10 )x(f rt 9 sw 7 sw = + ? () 2 fb r 1 out r 2 max15026 figure 2. adjustable output voltage
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 14 ______________________________________________________________________________________ connect an external resistor (r lim ) from lim to gnd to adjust the current-limit threshold. the relationship between the current-limit threshold (v ith ) and r lim is: where r lim is in k and v ith is in mv. an r lim resistance range of 6k to 60k corresponds to a current-limit threshold of 30mv to 300mv. use 1% tolerance resistors when adjusting the current limit to minimize error in the current-limit threshold. input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the switching circuitry. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents as defined by the following equation, i rms attains a maximum value when the input voltage equals twice the output voltage (v in = 2v out ), so i rms(max) = i load(max) /2. for most applications, non-tantalum capacitors (ceramic, aluminum, poly- mer, or os-con) are preferred at the inputs due to the robustness of non-tantalum capacitors to accom- modate high inrush currents of systems being pow- ered from very low-impedance sources. additionally, two (or more) smaller-value low-esr capacitors can be connected in parallel for lower cost. output capacitor the key selection parameters for the output capacitor are capacitance value, esr, and voltage rating. these para- meters affect the overall stability, output ripple voltage, and transient response. the output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor? esr caused by the current flowing into and out of the capacitor: v ripple ? v esr + v q the output voltage ripple as a consequence of the esr and the output capacitance is: where i p-p is the peak-to-peak inductor current ripple (see the inductor selection section). use these equa- tions for initial capacitor selection. decide on the final values by testing a prototype or an evaluation circuit. check the output capacitor against load-transient response requirements. the allowable deviation of the output voltage during fast load transients determines the capacitor output capacitance, esr, and equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a higher duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter (see the compensation section). the resistive drop across the esr of the output capacitor, the voltage drop across the esl ( v esl ) of the capaci- tor, and the capacitor discharge, cause a voltage droop during the load step. use a combination of low-esr tantalum/aluminum elec- trolytic and ceramic capacitors for improved transient load and voltage ripple performance. nonleaded capacitors and capacitors in parallel help reduce the esl. keep the maximum output voltage deviation below the tolerable limits of the load. use the following equa- tions to calculate the required esr, esl, and capaci- tance value during a load step: where i step is the load step, t step is the rise time of the load step, t response is the response time of the con- troller and f o is the closed-loop crossover frequency. compensation the max15026 provides an internal transconductance amplifier with the inverting input and the output avail- able for external frequency compensation. the flexibility of external compensation offers a wide selection of out- put filtering components, especially the output capaci- tor. use high-esr aluminum electrolytic capacitors for cost-sensitive applications. use low-esr tantalum or ceramic capacitors at the output for size sensitive applications. the high switching frequency of the max15026 allows the use of ceramic capacitors at the output. choose all passive power components to meet the output ripple, component size, and component cost esr v i c it v esl v esr step out step response q = = = e esl step step response o t i t f ? 1 3 v i esr v i cf i vv esr p p q pp out sw pp in o = = = ? ? ? ? 8 u ut sw out in fl v v ? ? ? ? ? ? ? ? ? ? ? ? ii vvv v rms load max out in out in = ? () () r v a lim ith = 10 50
requirements. choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. to choose the appropriate compensation network type, the power-supply poles and zeros, the zero crossover frequency, and the type of the output capacitor must be determined. in a buck converter, the lc filter in the output stage intro- duces a pair of complex poles at the following frequency: the output capacitor introduces a zero at: where esr is the equivalent series resistance of the output capacitor. the loop-gain crossover frequency (f o ), where the loop gain equals 1 (0db) should be set below 1/10th of the switching frequency: choosing a lower crossover frequency reduces the effects of noise pick-up into the feedback loop, such as jittery duty cycle. to maintain a stable system, two stability criteria must be met: 1) the phase shift at the crossover frequency f o , must be less than 180? in other words, the phase margin of the loop must be greater than zero. 2) the gain at the frequency where the phase shift is -180 (gain margin) must be less than 1. maintain a phase margin of around 60 to achieve a robust loop stability and well-behaved transient response. when using an electrolytic or large-esr tantalum output capacitor the capacitor esr zero f zo typically occurs between the lc poles and the crossover frequency f o (f po < f zo < f o ). choose type ii (pi?roportional-inte- gral) compensation network. when using a ceramic or low-esr tantalum output capacitor, the capacitor esr zero typically occurs above the desired crossover frequency f o , that is f po < f o < f zo . choose type iii (pid?roportional, integral, and derivative) compensation network. type ii compensation network (figure 3) if f zo is lower than f o and close to f po , the phase lead of the capacitor esr zero almost cancels the phase loss of one of the complex poles of the lc filter around the crossover frequency. use a type ii compensation network with a midband zero and a high-frequency pole to stabilize the loop. in figure 3, r f and c f intro- duce a midband zero (f z1 ). r f and c cf in the type ii compensation network provide a high-frequency pole (f p1 ), which mitigates the effects of the output high-fre- quency ripple. follow the instructions below to calculate the component values for the type ii compensation network in figure 3: 1) calculate the gain of the modulator (gain mod ), comprised of the regulator? pulse-width modulator, lc filter, feedback divider, and associated circuitry at the crossover frequency: where v in is the input voltage of the regulator, v ramp is the amplitude of the ramp in the pulse-width modulator, v fb is the fb input voltage set-point (0.591v typically, see the electrical characteristics table), and v out is the desired output voltage. the gain of the error amplifier (gain ea ) in midband fre- quencies is: gain ea = g m x r f where g m is the transconductance of the error amplifier. the total loop gain, which is the product of the modula- tor gain and the error amplifier gain at f o , is 1. so: solving for r f : 2) set a midband zero (f z1 ) at 0.75 x f po (to cancel one of the lc poles): f rc f z ff po 1 1 2 075 = = . r vflv v v g esr f ramp o out out fb in m = () 2 v v esr fl v v gr in ramp o out fb out mf = () 2 1 gain gain mod ea = 1 gain v v esr fl v v mod in ramp o out fb out = () 2 f f o sw 10 f esr c zo out = 1 2 f lc po out out = 1 2 max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller ______________________________________________________________________________________ 15
max15026 solving for c f : 3) place a high-frequency pole at f p1 = 0.5 x f sw (to attenuate the ripple at the switching frequency, f sw ) and calculate c cf using the following equation: type iii compensation network (see figure 4) when using a low-esr tantalum or ceramic type, the esr-induced zero frequency is usually above the tar- geted zero crossover frequency (f o ). use type iii com- pensation. type iii compensation provides three poles and two zeros at the following frequencies: two midband zeros (f z1 and f z2 ) cancel the pair of complex poles introduced by the lc filter: f p1 = 0 f p1 introduces a pole at zero frequency (integrator) for nulling dc output voltage errors: depending on the location of the esr zero (f zo ), use f p2 to cancel f zo , or to provide additional attenuation of the high-frequency output ripple: f p3 attenuates the high-frequency output ripple. place the zeros and poles so the phase margin peaks around f o . ensure that r f >>2/g m and the parallel resistance of r 1 , r 2 , and r i is greater than 1/g m . otherwise, a 180 phase shift is introduced to the response making the loop unstable. use the following compensation procedure: 1) with r f 10k , place the first zero (f z1 ) at 0.8 x f po . so: 2) the gain of the modulator (gain mod ), comprises the pulse-width modulator, lc filter, feedback divider, and associated circuitry at the crossover frequency is: gn v v fl c in ramp ooutout ai mod = () 1 2 2 gn v v in ramp ai mod = ( 2 = = . f r cc cc p f fcf fcf 3 1 2 = + f rc p ii 2 1 2 = f rc f crr z ff z ii 1 2 1 1 2 1 2 = = + () c rf c cf fsw f = ? 1 1 c rf f fpo = 1 2075 . low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 16 ______________________________________________________________________________________ v ref r 1 v out r 2 g m r f comp c f c cf figure 3. type ii compensation network v ref g m r 1 r 2 v out r i comp c i c cf r f c f figure 4. type iii compensation network
the gain of the error amplifier (gain ea ) in midband fre- quencies is: gain ea = 2 x f o x c 1 x r f the total loop gain as the product of the modulator gain and the error amplifier gain at f o is 1. so: solving for c i : 3) use the second pole (f p2 ) to cancel f zo when f po < f o < f zo < f sw /2. the frequency response of the loop gain does not flatten out soon after the 0db crossover, and maintains a -20db/decade slope up to 1/2 of the switching frequency. this is likely to occur if the output capacitor is a low-esr tantalum. set f p2 = f zo . when using a ceramic capacitor, the capacitor esr zero f zo is likely to be located even above 1/2 the switching frequency, f po < f o < f sw /2 < f zo . in this case, place the frequency of the second pole (f p2 ) high enough to not significantly erode the phase margin at the crossover frequency. for example, set f p2 at 5 x f o so that the contribution to phase loss at the crossover frequency f o is only about 11? f p2 = 5 x f po once f p2 is known, calculate r i: 4) place the second zero (f z2 ) at 0.2 x f o or at f po , whichever is lower, and calculate r 1 using the fol- lowing equation: 5) place the third pole (f p3 ) at 1/2 the switching fre- quency and calculate c cf : 6) calculate r 2 as: mosfet selection the max15026 step-down controller drives two external logic-level n-channel mosfets. the key selection parameters to choose these mosfets include: ?on-resistance (r ds(on) ) ?maximum drain-to-source voltage (v ds(max) ) ?minimum threshold voltage (v th(min) ) ?total gate charge (q g ) ?reverse transfer capacitance (c rss ) ?power dissipation the two n-channel mosfets must be a logic-level type with guaranteed on-resistance specifications at v gs = 4.5v. for maximum efficiency, choose a high-side mosfet that has conduction losses equal to the switching losses at the typical input voltage. ensure that the conduction losses at minimum input voltage do not exceed the mosfet package thermal limits, or vio- late the overall thermal budget. also, ensure that the conduction losses plus switching losses at the maxi- mum input voltage do not exceed package ratings or violate the overall thermal budget. ensure that the dl gate driver can drive the low-side mosfet. in particu- lar, check that the dv/dt caused by the high-side mosfet turning on does not pull up the low-side mosfet gate through the drain-to-gate capacitance of the low-side mosfet, which is the most frequent cause of cross-conduction problems. check power dissipation when using the internal linear regulator to power the gate drivers. select mosfets with low gate charge so that v cc can power both dri- vers without overheating the device. p drive = v cc x q g_total x f sw where q g_total is the sum of the gate charges of the two external mosfets. r v vv r fb out fb 21 = ? c c frc cf f sw f f = () ? 205 1 . r fc r zi i 1 2 1 2 = ? r fc i pi = 1 2 2 c vflc vr i ramp o out out in f = () 2 v v fc l in ramp ooutout 1 2 2 () gain gain mod ea = 1 max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller ______________________________________________________________________________________ 17
max15026 boost capacitor the max15026 uses a bootstrap circuit to generate the necessary gate-to-source voltage to turn on the high- side mosfet. the selected n-channel high-side mosfet determines the appropriate boost capaci- tance value (c bst in the typical application circuits ) according to the following equation: where q g is the total gate charge of the high-side mosfet and v bst is the voltage variation allowed on the high-side mosfet driver after turn-on. choose v bst so the available gate-drive voltage is not signifi- cantly degraded (e.g. v bst = 100mv to 300mv) when determining c bst . use a low-esr ceramic capacitor as the boost flying capacitor with a minimum value of 100nf. power dissipation the maximum power dissipation of the device depends on the thermal resistance from the die to the ambient environment and the ambient temperature. the thermal resistance depends on the device package, pcb cop- per area, other thermal mass, and airflow. the power dissipated into the package (p t ) depends on the supply configuration (see the typical application circuits ). use the following equation to calculate power dissipation: p t = (v in - v cc ) x i ldo + v drv x i drv + v cc x i in where i ldo is the current supplied by the internal regu- lator, i drv is the supply current consumed by the dri- vers at drv, and i in is the supply current of the max15026 without the contribution of the i drv , as given in the typical operating characteristics . for example, in the application circuit of figure 5, i ldo = i drv + i in and v drv = v cc so that p t = v in x (i drv + i in ). use the following equation to estimate the temperature rise of the die: t j = t a + (p t x ja ) where ja is the junction-to-ambient thermal imped- ance of the package, p t is power dissipated in the device, and t a is the ambient temperature. the ja is 24.4?/w for 14-pin tdfn package on multilayer boards, with the conditions specified by the respective jedec standards (jesd51-5, jesd51-7). an accurate estimation of the junction temperature requires a direct measurement of the case temperature (t c ) when actual operating conditions significantly deviate from those described in the jedec standards. the junction tem- perature is then: t j = t c + (p t x jc ) use 8.7?/w as jc thermal impedance for the 14-pin tdfn package. the case-to-ambient thermal imped- ance ( ca ) is dependent on how well the heat is trans- ferred from the pcb to the ambient. solder the exposed pad of the tdfn package to a large copper area to spread heat through the board surface, minimizing the case-to-ambient thermal impedance. use large copper areas to keep the pcb temperature low. pcb layout guidelines place all power components on the top side of the board, and run the power stage currents using traces or copper fills on the top side only. make a star connec- tion on the top side of traces to gnd to minimize volt- age drops in signal paths. keep the power traces and load connections short, especially at the ground terminals. this practice is essential for high efficiency and jitter-free operation. use thick copper pcbs (2oz or above) to enhance efficiency. place the max15026 adjacent to the synchronous recti- fier mosfet, preferably on the back side, to keep lx, gnd, dh, and dl traces short and wide. use multiple small vias to route these signals from the top to the bot- tom side. use an internal quiet copper plane to shield the analog components on the bottom side from the power components on the top side. make the max15026 ground connections as follows: create a small analog ground plane near the device. connect this plane to gnd and use this plane for the ground connection for the v in bypass capacitor, com- pensation components, feedback dividers, v cc capaci- tor, rt resistor, and lim resistor. use kelvin sense connections for lx and gnd to the synchronous rectifier mosfet for current limiting to guarantee the current-limit accuracy. route high-speed switching nodes (bst, lx, dh, and dl) away from the sensitive analog areas (rt, comp, lim, and fb). group all gnd-referred and feedback compo- nents close to the device. keep the fb and compensation network as small as possible to prevent noise pickup. c q v bst g bst = low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 18 ______________________________________________________________________________________
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller ______________________________________________________________________________________ 19 typical application circuits r5 10k r3 4.02k r1 11.8k dh lx q2 l1 1.4 h bst dl enable pgood v in drv gnd rt in v cc pgood lim en comp fb r7 4.02k r6 15.4k r4 27k r1* *r1 is a small-value resistor to decouple switching transients caused by the mosfet driver (2.2 ). c6 2.2 f c1 330 f panasonic eeefcie331p 4.5v to 28v c10 4.7 f c7 68pf c9 0.022 f c8 68pf c11 1500pf c4 470 f sanyo 4c54701 c5 22 f c3 0.47 f q1 ( ) v out coilcraft mss1278-142ml max15026 on-semiconductor ntmfs4835ntig ( ) on-semiconductor ntmfs4835ntig single 4.5v to 28v supply operation figure 5 shows an application circuit for a single 4.5v to 28v power-supply operation. figure 5. v in = 4.5v to 28v
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 20 ______________________________________________________________________________________ typical application circuits (continued) single 4.5v to 5.5v supply operation figure 6 shows an application circuit for a single 4.5v to 5.5v power-supply operation. figure 6. v cc = v in = v drv = 4.5v to 5.5v r1 r3 r lim dh lx l1 bst dl enable pgood v in drv gnd rt in v cc pgood lim en comp fb r2 rt c1 4.5v to 5.5v c4 c3 c2 q2 c f1 c bst q1 v out max15026
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller ______________________________________________________________________________________ 21 typical application circuits (continued) r1 r3 r lim dh lx l1 bst dl enable v aux 4.5v to 5.5v pgood v in +12v drv gnd rt in v cc pgood lim en comp fb r2 rt c1 c4 c3 c2 q2 c f1 c bst q1 v out max15026 auxiliary 5v supply operation figure 7 shows an application circuit for a +12v supply to drive the external mosfets and an auxiliary +5v supply to power the device. figure 7. operation with auxiliary 5v supply
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller 22 ______________________________________________________________________________________ chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 14 tdfn-ep t1433+2 21-0137 90-0063
max15026 low-cost, small, 4.5v to 28v wide operating range, dc-dc synchronous buck controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/08 initial release 1 5/09 revised general description , ordering information , absolute maximum ratings , electrical characteristics , power-good output (pgood) section, and typical application circuits 1?, 10, 15, 19 2 9/10 added max15026c; revised general description , ordering information , electrical characteristics , typical operating characteristics , and startup into a prebiased output sections 1?, 10 3 4/11 added automotive part to ordering information , absolute maximum ratings , and electrical characteristics 1, 2, 3

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